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| 09:50:07 | zahary_ | Araq, FYI: http://nwcpp.org/talks/2009/Ownership_Systems_against_Data_Races.pdf |
| 09:50:47 | zahary_ | from here: http://bartoszmilewski.com/2009/09/22/ownership-systems-against-data-races/ |
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| 14:12:46 | jbe_ | does someone know why i get a segfault when i use the queue implementation and call add on a field, like: add(obj.queue, item)? |
| 14:13:08 | dom96 | did you initialise the queue? |
| 14:13:15 | jbe_ | yup |
| 14:13:21 | jbe_ | sample: https://gist.github.com/jbe/6207385 |
| 14:16:15 | dom96 | hrm, looks like a bug |
| 14:16:47 | jbe_ | i thought so too |
| 14:17:08 | jbe_ | should i add it to the tracker? |
| 14:18:18 | dom96 | sure |
| 14:23:05 | dom96 | it's odd, if you then do 'w.names = initQueue[string]()' it works |
| 14:31:23 | jbe_ | yeah, i added an issue |
| 14:31:35 | dom96 | thanks |
| 14:31:57 | jbe_ | nimrod is completely awesome by the way |
| 14:32:22 | dom96 | nice to hear you say that :) |
| 14:32:30 | dom96 | spread the word if you can :D |
| 14:33:27 | jbe_ | am already doing.. and i will make a little shrine for araq on my balcony or something |
| 14:33:35 | dom96 | hehe |
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| 17:44:13 | Mat2 | hello |
| 17:45:50 | Araq | hi Mat2 |
| 17:50:16 | Araq | Mat2: you can avoid a jump table by doing 'goto opcode*256'; you need to ensure every handler doesn't span more than 256 bytes then and is aligned properly |
| 17:50:45 | Araq | ever tried this approach? it's impossible to do in C I think |
| 17:52:03 | Araq | this way you can keep the opcode in a few bits of the instruction and don't waste a full word for full threading |
| 17:54:32 | Mat2 | yes, I have done that before for a small VM written in assembler |
| 17:55:25 | Mat2 | with some assembler hacking, it's also possible in C (but of course not in a platform-independent way) |
| 17:56:39 | Araq | was it worth it? |
| 17:56:47 | Mat2 | for IA32 no |
| 17:58:07 | Araq | did you compare against a jump table or against full threading? |
| 17:58:27 | Mat2 | I compared it against direct threading |
| 18:00:39 | Mat2 | it is only effective by precalculating the branch target in the handler routines and the BTB get out of sync the same way as for DTC (ca. 50% mispredictions) |
| 18:02:35 | Mat2 | because the only way on IA32 is either selfmodifying code (with desastrous results because of the out-of-order pipelined design) or branching though indirect register |
| 18:03:10 | Mat2 | e.g. jmp <reg> |
| 18:03:21 | Araq | yeah but the idea is to minimize cache pressure |
| 18:03:52 | Araq | avoiding the jump table so that the cache can hold other things |
| 18:04:41 | Mat2 | ok, BTB mispredictions costs much more clock cycles (I have counted more than 100 in some measures, mean 25-30) |
| 18:07:20 | Mat2 | that depends on the number of pipeline stages |
| 18:10:34 | Mat2 | and caches are rather large (for Intel cpu's) |
| 18:19:10 | Mat2 | anyhow, I do not know what kind of large memory allocations requires cache-preloading beside the VM |
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| 21:00:26 | dom96 | So I just submitted this: https://github.com/logicchains/Levgen-Parallel-Benchmarks/pull/2 |
| 21:00:47 | dom96 | Hopefully soon we will see a blog post which shows Nimrod coming out on top in terms of speed and sexiness :D |
| 21:02:21 | Araq | sure ... |
| 21:02:31 | Araq | we've seen lots of these already |
| 21:33:53 | EXetoC | :> |
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| 21:54:13 | Mat2 | get some sleep, ciao |
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| 22:12:03 | reactormonk | dom96, happy? |
| 22:17:13 | dom96 | reactormonk: hrm? |
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| 22:30:42 | reactormonk | Looks like I need to recreate the PR |
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| 22:50:10 | dom96 | indeed |
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