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| 06:55:13 | DAddYE | congrats Araq: https://github.com/DAddYE/node.nim#how-fast-it-is |
| 06:58:24 | DAddYE | congrats Araq: https://github.com/DAddYE/node.nim#how-fast-is-it |
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| 10:03:30 | dom96 | 'morning |
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| 16:39:09 | DAddYE | morning |
| 16:58:26 | EXetoC | hi |
| 17:47:24 | dom96 | hello |
| 17:53:42 | EXetoC | åäö! |
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| 18:21:36 | dom96 | DAddYE: great job on those benchmarks btw :) |
| 18:21:56 | DAddYE | dom96: thanks! |
| 18:22:16 | DAddYE | nothing scientific just to get an idea |
| 18:22:31 | DAddYE | how much faster than go we are hahaha |
| 18:22:50 | dom96 | :D |
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| 20:34:03 | Mat2 | hello |
| 20:35:02 | Araq | hi Mat2 |
| 20:35:47 | Araq | I skimmed your VM somewhat more and wonder why you don't have a pletora of load/store instructions |
| 20:36:01 | Araq | does Forth lack arrays? ;-) |
| 20:36:10 | Mat2 | hi Araq |
| 20:38:37 | Mat2 | instruction bundling makes special (indexed) load-store operations needless |
| 20:39:14 | Araq | please explain |
| 20:40:10 | Mat2 | in a canonical MISC design exist only one instruction for immediate-pushes onto the data stack (LIT) |
| 20:40:38 | Mat2 | all other instructions operate with the top-of-stack |
| 20:41:21 | Mat2 | so indexed addressing (a stack-frame for example) ofen looks like this: |
| 20:41:49 | Mat2 | LI address, over offset, add, ld |
| 20:42:22 | Mat2 | this build up exact one combined opcode in my vm |
| 20:43:06 | Mat2 | dependent on dispatching up to 16 instructions can be executed in one interpreter iteration |
| 20:43:28 | Araq | hmm must have missed that 'ld' instruction |
| 20:44:06 | Mat2 | yes |
| 20:45:06 | Mat2 | think of my vm as some kind of VLIW design in software |
| 20:47:15 | Mat2 | ^often |
| 20:49:00 | Mat2 | there are some similarities (like instruction-bundling, seperation of instruction and immediate parameters, only one unified code format) |
| 20:51:04 | Mat2 | the main difference is that VLIW architectures bundles instructions for different execution-units where in my vm each slot addresses one unified virtual one |
| 20:51:37 | Araq | yeah got it |
| 20:52:33 | Mat2 | I have a mode where each slot (consisting of two bundled instructions) is executed parallel for supporting fine-grained multiporcessing but is is then up to the compiler to pack independent opcodes |
| 20:52:47 | Mat2 | ^multiprozessing |
| 20:53:35 | Mat2 | (each slot addresses private data and return stacks of course, memory accesses are serialized round-robin) |
| 20:54:58 | Araq | that shouldn't help :P |
| 20:55:25 | Mat2 | its an experiment |
| 20:55:38 | Araq | running memory accesses in parallel is where the gain comes from on modern CPUs I guess |
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| 20:57:08 | Mat2 | there is an interesting measurements published in the last C't which proves you right |
| 20:57:42 | Mat2 | however, I have added this mode because some MCUs like the propeller chip is working in this scheme |
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| 21:02:14 | EXetoC | the last what? |
| 21:04:34 | Mat2 | C't (Computer & Technik). An traditional computer magazine in Germany for computer enthusiasts |
| 21:05:05 | Mat2 | (somewhat similar to the byte magazin in the US) |
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| 21:35:58 | * | Mat2 found these article: http://scottlocklin.wordpress.com/2013/07/28/ruins-of-forgotten-empires-apl-languages/ |
| 21:40:18 | Mat2 | get some sleep, ciao |
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| 21:52:36 | NimBot | Araq/Nimrod master 11b5080 Araq [+0 ±2 -0]: 'nimrod pretty' command: next steps |
| 21:52:36 | NimBot | Araq/Nimrod master fa496b3 Araq [+0 ±2 -0]: 'nimrod pretty': next steps, doesn't work yet |
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